Dielectric breakdown I: A review of oxide breakdown

This paper gives an overview of the dielectric breakdown in thin oxide layers on silicon. First test methods are discussed, followed by their application to the estimation of the oxide lifetime. The main part of the paper is devoted to the physical background of the intrinsic breakdown. Finally, defect-related or extrinsic breakdown is discussed

Dielectric breakdown II: Related projects at the University of Twente

In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the inherent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties

Cross-Bridge Kelvin resistor structures for reliable measurement of low contact resistances and contact interface characterization

The parasitic factors that strongly influence the measurement accuracy of Cross-Bridge Kelvin Resistor (CBKR) structures for low specific contact resistances (rhoc) have been extensively discussed during last few decades and the minimum of the rhoc value, which could be accurately extracted, was estimated. We fabricated a set of various metal-to-metal CBKR structures with different geometries, i.e., shapes and dimensions, to confirm this limit experimentally and to create a method for contact metal-to-metal interface characterization. As a result, a model was developed to account for the actual current flow and a method for reliable rhoc extraction was created. This method allowed to characterize metal-to-metal contact interface. It was found that in the case of ideal metal-to-metal contacts, the measured CBKR contact resistance was determined by the dimensions of the two-metal stack in the area of contact and sheet resistances of the metals used

Cross-bidge Kelvin resistor (CBKR) structures for measurement of low contact resistances

A convenient test structure for measurement of the specific contact resistance (ρc) of metal-semiconductor junctions is the CBKR structure. During last few decades the parasitic factors which may strongly affect the measurements accuracy for ρc < 10-6 Ω • cm2 have been sufficiently discussed and the minimum of the ρc to be measured using CBKR structures was estimated. We fabricated a set of CBKR structures with different geometries to confirm this limit experimentally. These structures were manufactured for metal-to-metal contacts. It was found that the extracted CBKR values were determined by dimensions of the two-metal stack in the contact area and sheet resistances of the metals used. \ud Index Terms—Contact resistance, cross-bridge Kelvin resistor (CBKR), sheet resistance, test structures, metal, silico

Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd ¿ 25 C/cm2), low charge trapping and low leakage currents

An intensive study of LPCVD silicon morphology and texture for non volatile memory

Results of an intensive study by means of XRD, SEM, AFM and TEM of the microstructure (i.e. the texture and morphology) of LPCVD silicon layers as a function of different process parameters are described. The influence of different deposition parameters, like partial and total pressure, doping, deposition and anneal temperature is shown. In particular the roughness of the silicon surface is investigated. The relation of surface roughness to the electrical properties of dielectrics, grown on these silicon layers, is briefly discussed